As the degree of integration of semiconductor devices has increased, an increase in wiring resistance has become a problem. The materials of gate electrodes primarily used in memory processes have shifted from conventional polysilicon doped with impurities to silicide films that make it possible to lower the resistance value and polymetal structures in which metal materials such as tungsten and the like are stacked on top of polysilicon. Here, silicide films (also referred to as silicate films) are films that are formed by the fusion of metals and silicon. Polymetal structures are structures in which metals are stacked on top of polysilicon, and are structures in which a barrier metal is inserted between the polysilicon and metal in order to prevent silicate formation.
The polymetal structures and silicide films mentioned above will be described using as an example the gate electrodes shown in FIG. 4g. These electrodes are parts of a flash memory or DRAM. Furthermore, FIGS. 4(a) and 4(c) show portions of the structures of flash memories, and FIG. 4(b) shows a portion of the structure of a DRAM.
FIG. 4(a) shows one example in which a polymetal structure is applied to the gate electrode (control electrode) of a flash memory. In order to form a polymetal structure, a surface of a silicon substrate 100 constituting a dynamic layer is thermally oxidized, and a silicon dioxide film (SiO2 film) 110 used for gate insulation is formed; a polysilicon film (poly-Si film) 120 used as a floating gate is deposited on top of this SiO2 film. A poly-Si film 140 used as a gate electrode is stacked on top of this poly-Si film 120, with an SiO2/Si3N4/SiO2 film (insulating film having an ONO structure) 130 or the like interposed as an insulating film. In order to lower the resistance, a tungsten nitride (WN) film 150 is formed as a barrier metal, and a tungsten (W) film 160 is deposited as a metallic thin film on top of this. Subsequently, the stacked films described above are patterned by a dry etching method, so that a structure having a polymetal gate 200 having a stacked structure is formed on the gate region between the source region 80 and drain region 90 as shown in FIG. 4(a).
FIG. 4(b) shows one example in which a polymetal structure is applied to the gate electrode of a DRAM. This example differs from FIG. 4(a) in that there is no poly-Si film 120 or insulating film 130 having an ONO structure; the remaining structure is the same. Furthermore, FIG. 4(c) shows an example in which a silicide film, e.g., a tungsten silicide (WSi) film 170, is used instead of the polymetal structure in FIG. 4(a). This example differs from FIG. 4(a) in that a WSi film 170 is deposited on top of the poly-Si film 140 formed on a surface of the insulating film 130 having an ONO structure.
The dry etching method used to pattern stacked films is a working operation in which a surface of the stacked films is physically shaved off by sputtering. In the polymetal gate structure shown in FIG. 4(a) as an example, damage is inflicted on the surface of the silicon substrate 100 in the source region 80, drain region 90, and the like, and on the side surfaces of the thermal oxidation film (SiO2 film) 110, poly-Si film 120, insulating film 130 having an ONO structure, poly-Si film 140, and the like, and this leads to an increase in the wiring resistance and an increase in the leak current.
In cases in which impurity-doped polysilicon is used as the material of the gate electrode, in order to recover from this damage inflicted on the surface of the silicon substrate 100 and side surfaces of the thermal oxidation film and the like by dry etching, and in order to form a protective film, the moisture generated on the outside of the processing chamber is usually supplied to the interior of the processing chamber at normal pressure or under reduced pressure, and a thermal oxidation film used for protection is formed on the surface of the silicon substrate 100 and the side surfaces of the thermal oxidation film and the like by this moisture (for example, see patent document 1).
Patent document 1: Japanese Laid-Open Patent Application No. 2002-110667